1. Field of the Invention
The invention relates to a CMOS semiconductor device including a gate electrode into which p-type impurities are heavily doped and a gate electrode into which n-type impurities are heavily doped, and further to a method of fabricating the same. More particularly, the invention relates to a CMOS semiconductor device capable of suppressing reduction in a dielectric voltage of a gate insulating film.
2. Description of the Related Art
In these days, a gate electrode has been designed to having a smaller width as LSI has been more highly integrated. A smaller width causes a gate electrode to have a higher resistance. As a solution to such a higher resistance of a gate electrode, a gate electrode has been conventionally composed of a polycide wiring layer comprised of a polysilicon layer and a silicide layer. As a silicide layer has been used a tungsten silicide layer having resistivity of about 70 .mu..OMEGA.-cm.
As LSI has been required to fabricate in a smaller size, a gate electrode has been required to have a smaller width, and in addition, the tungsten silicide layer has been required to have a smaller thickness. As a result, a resistance of the polycide wiring layer has increased in inverse proportion to the second power of a scale-down ratio of the polycide wiring layer. For this reason, a titanium silicide layer is presently used in place of a tungsten silicide layer, because a titanium silicide layer has smaller resistivity than that of a tungsten silicide layer. A titanium silicide layer has resistivity of about 15 .mu..OMEGA.-cm, and is generally formed by means of salicide process. In salicide process, both a gate electrode and source/drain diffusion layers are concurrently silicided. The salicide process is now widely used, in particular, for fabricating a semiconductor device having a gate length of 0.25 .mu.m or smaller.
A conventional pMOSFET has been fabricated as a transistor having a buried channel. However, if such a conventional pMOSFET was formed as having a gate length of 0.25 .mu.m or smaller, there occurred significant short channel effect. For this reason, pMOSFET is predominantly formed as a transistor having a channel at a surface rather than a transistor having a buried channel. That is, an n-n gate type, which has been predominantly used, is substituted by a p-n gate type in CMOS semiconductor device.
Hereinbelow is explained a conventional method of fabricating CMOS semiconductor device including a p-n type gate by means of titanium salicide process. FIGS. 1A to 1E are cross-sectional views of CMOS semiconductor device, illustrating respective steps of a conventional method of fabricating the same.
First, as illustrated in FIG. 1A, field oxide films 102 are formed at a surface of a p-type silicon substrate 101 in selected regions. Then, p-well 103 is formed in the silicon substrate 101 in a region where nMOSFET is to be fabricated, and n-well 104 is formed in the silicon substrate 101 in a region where pMOSFET is to be fabricated. Then, the p-well 103 and n-well 104 are both covered at a surface thereof with a gate oxide film 105.
Then, as illustrated in FIG. 1B, a polysilicon layer having a shape of a gate electrode is formed on the gate oxide film 105. Thereafter, a portion of the gate oxide film 105 which is not covered with the polysilicon layer is removed. Then, n-type ions are implanted into a region where nMOSFET is to be fabricated, and p-type ions are implanted into a region where pMOSFET is to be fabricated, to thereby form diffusion layers in both the regions.
Then, a sidewall 113 is formed on a side surface of the polysilicon layer. Thereafter, n-type ions are implanted into the region where nMOSFET is to be fabricated, by means of photolithography, at a higher concentration than a concentration at which n-type ions have been previously implanted to the region, to thereby form source/drain n.sup.+ layers 114. Similarly, p-type ions are implanted into the region where pMOSFET is to be fabricated, by means of photolithography, at a higher concentration than a concentration at which p-type ions have been previously implanted to the region, to thereby form source/drain p.sup.+ layers 115. At the same time, LDDn layer 111 having a lower impurity concentration than that of the source/drain n.sup.+ layers 114 is also formed below the sidewall 113 and adjacent to the source/drain n.sup.+ layers 114, and LDDp layer 112 having a lower impurity concentration than that of the source/drain p.sup.+ layers 115 is also formed below the sidewall 113 and adjacent to the source/drain p.sup.+ layers 115.
By the above-mentioned second ion-implantation, n-type ions are implanted into the polysilicon layer in the region where nMOSFET is to be fabricated, with the result that an n.sup.+ gate electrode 116 is formed above the p-well 103, and p-type ions are implanted into the polysilicon layer in the region where pMOSFET is to be fabricated, with the result that a p.sup.+ gate electrode 117 is formed above the n-well 104.
Then, as illustrated in FIG. 1C, a titanium layer 118 is deposited all over the product by sputtering, for instance.
Then, as illustrated in FIG. 1D, the product is thermally annealed, for instance, at about 700 degrees centigrade in a nitrogen atmosphere, to thereby cause the titanium layer 118 to react with the n.sup.+ gate electrode 116, the p.sup.+ gate electrode 117, the source/drain n.sup.+ layer 114, and the source/drain p.sup.+ layer 115. As a result, an n.sup.+ titanium silicide layer 116a is formed in an upper part of the n.sup.+ gate electrode 116, a p.sup.+ titanium silicide layer 117a is formed in an upper part of the p.sup.+ gate electrode 117, a source/drain n.sup.+ titanium silicide layer 114a is formed on the source/drain n.sup.+ layer 114, and a source/drain p.sup.+ titanium silicide layer 115a is formed on the source/drain p.sup.+ layer 115.
After non-reacted portions of the titanium layer 118 are removed, the product is thermally annealed at 850 degrees centigrade, for instance, in a nitrogen atmosphere to thereby reduce resistances of the n.sup.+ titanium silicide layer 116a, the p.sup.+ titanium silicide layer 117a, the source/drain n.sup.+ titanium silicide layer 114a, and the source/drain p.sup.+ titanium silicide layer 115a. Thus, there is completed CMOS semiconductor device, as illustrated in FIG. 1E.
In the thus fabricated CMOS semiconductor device, when the titanium silicide layers 116a, 117a, 114a, and 115a are thermally annealed for reducing a resistance thereof, titanium atoms diffuse in the gate electrodes 116 and 117, and reach the gate oxide film 105, resulting in a problem of reduction in dielectric voltage of the gate oxide film 105.
In order to solve this problem, Japanese Unexamined Patent Publication No. 63-177538 having been published on Jul. 21, 1988 has suggested a semiconductor device capable of preventing reduction in dielectric voltage of a gate oxide film. FIG. 2 is a cross-sectional view of a semiconductor device suggested in the Publication.
The suggested semiconductor device includes field oxide films 202 formed on a p-type silicon substrate 201 in selected regions, and a gate oxide film 205 formed between the field oxide films 202. A polysilicon film 203 is formed on both the field oxide film 202 and the gate oxide film 205. A silicon nitride film 204 is formed over the polysilicon layer 203. As illustrated in FIG. 2, the silicon nitride film 204 is formed above the field oxide films 202 with openings. A titanium silicide layer 210 is formed as a top layer entirely covering a product therewith. The titanium silicide layer 210 is in electrical connection with the polysilicon layer 203 through the openings of the silicon nitride film 204.
In accordance with the semiconductor device having the above-mentioned structure, since the silicon nitride film 204 is formed between the polysilicon layer 203 of which a gate electrode is formed, and the titanium silicide layer 210, it is possible to prevent titanium atoms contained in the titanium silicide layer 210 from reaching the gate oxide film 205.
However, there is a problem that it is not practical to apply the above-mentioned semiconductor device illustrated in FIG. 2 to a CMOS semiconductor device having a p-n type gate. As mentioned earlier, in a conventional process of fabricating a CMOS semiconductor device having a p-n type gate, ion-implantation and thermal annealing are applied to the polysilicon layer from which a gate electrode is formed, simultaneously with the formation of source/drain regions, in order to provide electrical conductivity to the polysilicon layer.
However, since the silicon nitride film 204 prevents diffusion of impurities into the polysilicon layer 203, a sufficient amount of impurities cannot be supplied to an interface between the polysilicon layer 203 and the gate oxide film 205, resulting in a gate electrode that is significantly depleted. This causes reduction in on-current.
Japanese Unexamined Patent Publication No. 7-94731 having been published on Apr. 7, 1995 has suggested a semiconductor device including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film and comprised of a polysilicon layer, a barrier layer, and a refractory metal layer. The refractory metal film is covered at an upper surface and/or a side surface thereof with a refractory silicide layer, and is further covered at the upper surface and/or the side surface with a silicon nitride film with the above-mentioned refractory silicide layer being sandwiched between the refractory metal film and the silicon nitride film.
Japanese Unexamined Patent Publication No. 7-221097 having been published on Aug. 18, 1995 has suggested a semiconductor device including a silicon substrate, a gate oxide film formed on the silicon substrate, an amorphous silicon film formed on the gate oxide film by chemical vapor deposition (CVD), and a titanium silicide film formed on the amorphous silicon film by sputtering. By implanting oxygen ions into the amorphous silicon film, SiOx film is formed in the amorphous silicon film, followed by thermal annealing to thereby change the amorphous silicon film into a polysilicon film.